This invention relates generally to comparator circuits and more particularly to fully differential comparator circuits (differential input, reference, and output) and their application in analog-to-digital converters ("ADCs").
A conventional single-ended comparator 10 (single-ended input, reference, and output) is shown as a circuit symbol and in schematic form in FIG. 1. The triangular circuit symbol shows a positive input at node 1, a negative input at node 2, and an output at node 3. Either the positive input or the negative input can be used as the input or reference. Generally, the positive input serves as the single-ended nput, while the negative input is coupled to a source of reference voltage, resulting in a non-inverted output. The circuit symbol is labeled "comp". In schematic form, conventional comparator 10 is shown to include a pair of emitter-coupled NPN bipolar transistors QS and QR. The base of transistor QS is node 1, the positive input, which is labeled "SIG" and receives an analog signal input. The base of transistor QR is node 2, the negative input, which is labeled "REF" and receives a reference input voltage. Transistors QS and QR are biased via constant current source IEE, which is in turn coupled to a source of negative supply voltage VEE. The collector of transistor QS is coupled to a source of positive supply voltage VCC, while the collector of transistor QR is coupled to VCC through load resistor RL to form the comparator output voltage. The junction of the collector of transistor QR and load resistor RL is node 3, which is labeled "OUT" and provides the comparator voltage output signal. Note that SIG, REF, and OUT are all single-ended voltages. Note further that the input current at the base of transistors QS and QR are different (one is substantially zero, the other approximately equal to IEE/beta, wherein beta is transistor current gain), depending upon the logic state of the comparator.
A comparator bank and series resistor string for a "flash" ADC using eight conventional single-ended comparators is shown in FIG. 2. The comparator bank is coupled to the input signal SIG at node 16, which has a specified operating range of, for example, -4 to +4 volts. Comparator reference voltages are generated by the internal nodes of a serially-connected resistor string including resistors R1 through R9. The first resistor in the string, R1, is coupled to a lower reference voltage, REFN at node 14, which corresponds to the lower bound of the input signal, viz. -4 volts. Similarly, the last resistor in the string, R9, is coupled to an upper reference voltage, REFP at node 12, which corresponds to the upper bound of the input signal, viz. +4 volts. The internal nodes of the resistors string, nodes 20 through 27, generate a series of reference voltages that are uniformly spaced across the input signal range. The resistors have the relative values shown, i.e. resistors R2 through R8 have a relative value of unity, whereas the first and last resistors R1 and R9 have a relative value of one-half. The reference voltages on nodes 20 through 27 thus range from -3.5 volts at node 20 to +3.5 volts at node 27, and are equally spaced apart in one volt steps. The absolute value of the resistors are chosen according to power consumption, input bias current, and accuracy specifications.
Eight comparators, corresponding to the eight internal reference voltages are connected to the resistor string and to the input signal, and are labeled "C-3.5" through "C+3.5". The positive input of each of the comparators is coupled to the input signal node 16. The negative input of each of the comparators is coupled to the corresponding reference voltage. For example, the negative input of comparator C+0.5 is coupled to node 24, which has a reference voltage value of 0.5 volts. The outputs of the comparators provide thermometer scale data at output nodes D0 through D7. The digital data at node D0 is the least significant bit corresponding to an input signal greater than 3.5 volts for a logic one, and an input signal less than -3.5 volts for a logic zero. The digital data at node D7 is the most significant bit corresponding to an input signal more positive than 3.5 volts for a logic one, and an input signal less than 3.5 volts for a logic zero.
When the single-ended comparator 10 shown in FIG. 1 is used in the comparator bank of FIG. 2, inaccuracies can result. The loading of the resistor string with the input bias currents of the comparator can affect the precise linear distribution of the reference voltages over the input signal range, resulting in a parabolic response known as "droop." In addition to resistor string loading, the single-ended design of the comparator increases the susceptibility to common-mode signals, increases distortion, and has a nonlinear delay that is a function of input signal level.
What is desired is a fully differential comparator that, by design, eliminates the problems of a single-ended comparator and is therefore useful in the comparator bank of an ADC, as well as other applications.